1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a power-on resetting circuit and a method for initializing the semiconductor integrated circuit.
2. Description of the Related Art
Generally, a semiconductor integrated circuit has a power-on resetting circuit that generates a power-on reset signal. Malfunction of the semiconductor integrated circuit can be prevented by generating a power-on reset signal when the power supply is switched on and initializing the internal circuits. This type of a power-on resetting circuit detects, by utilizing the threshold voltage of a transistor, when the power supply voltage rises to a predetermined value, and varies (inactivates) the logic level of the power-on reset signal. The internal circuits are initialized in an activating period until the level of the power-on reset signal varies, and commences normal operation after the power-on reset signal is inactivated.
Recently, the transistor structure of the semiconductor integrated circuit has been further refined. Since the channel length of a transistor is shortened, the fluctuation width of the threshold voltage of the transistor is increased due to a short channel effect. The threshold voltage of the transistor varies, depending on the manufacturing conditions of the semiconductor integrated circuit, the chip position on the wafer, and the wafer position of production lots. If the fluctuation width of the threshold voltage is increased, deviation of inactivation timings of the power-on reset signal is also increased.
Also, the operation voltage of the semiconductor integrated circuit is lowered, and the power supply voltage supplied from the exterior is also lowered. Since the threshold voltage of the transistor scarcely depends on the power supply voltage, the ratio of the threshold voltage of the transistor with respect to the power supply voltage is increased. Resultantly, as described above, the deviation in inactivation timings of the power-on reset signal is increased.
As a result, for example, where the inactivation timing of the power-on reset signal shifts to the advanced side, the resetting period to initialize the internal circuits is shortened, and there is a fear that the internal circuits are not normally initialized. Where the inactivation timing of the power-on reset signal shifts to the delayed side, there is a fear that the logic level of the power-on resetting signal will not change. At this time, the power-on reset signal usually enters the activating state. Therefore, the internal circuits are always initialized, and they do not normally operate.
It is an object of the invention to initialize internal circuits by reliably generating a power-on reset signal without depending on the characteristics of a transistor.
According to one of the aspects of a semiconductor integrated circuit of the present invention, the semiconductor integrated circuit is provided with a plurality of sub reset signal generators and a main reset signal generator. The sub reset signal generators respectively generate sub power-on reset signals whose timings differ from each other. The main reset signal generator generates a main power-on reset signal according to at least one from any of the sub power-on reset signals. Therefore, even where the characteristics of elements that constitute the semiconductor integrated circuit change due to changes in the manufacturing conditions of the semiconductor integrated circuit, one of the sub power-on reset signals is generated at a normal timing. As a result, the main reset signal generator is able to generate a main power-on reset signal by using a normal sub power-on reset signal. That is, it is possible to constitute a power-on resetting circuit having a wide operation margin, wherein the internal circuits can be initialized without fault.
According to another aspect of a semiconductor integrated circuit of the present invention, the main power-on reset signal generator has pulse generators corresponding to the respective sub power-on reset signals. The pulse generators respectively generate pulses synchronizing with transition edges of the sub power-on reset signals. The main power-on reset signal can be easily generated by synthesizing these pulses.
According to still another aspect of a semiconductor integrated circuit of the present invention, the semiconductor integrated circuit is provided with a sub power-on reset signal generator, which generates sub power-on reset signals, and a main reset signal generator. The main reset signal generator generates a main power-on reset signal according to at least one of sub power-on reset signal and an external power-on reset signal supplied through a reset terminal. That is, it can generate a main power-on reset signal by using not only a sub power-on reset signal but also an external power-on reset signal supplied through the reset terminal, whereby the internal circuits can be initialized without fault.
According to yet another aspect of a semiconductor integrated circuit of the present invention, the semiconductor integrated circuit is provided with a plurality of sub reset signal generators and a main reset signal generator. The sub reset signal generators respectively generate sub power-on reset signals whose timings differ from each other. The main reset signal generator generates a main power-on reset signal according to at least one from any of a plurality of sub power-on reset signals and the external power-on reset signal supplied through the reset terminal. That is, the main signal generator can generate a main power-on reset signal by using a normal signal among a plurality of power-on reset signals.
According to another aspect of a semiconductor integrated circuit of the present invention, the main reset signal generator respectively generates pulses synchronizing with transition edges of the sub power-on reset signal(s) and an external power-on reset signal. The main power-on reset signal can be easily synthesized by using these pulses.
According to one aspect of, a method for initializing a semiconductor integrated circuit of the present invention, a plurality of power-on reset signals can be generated according to sub power-on reset signals whose timings differ from each other. And, internal circuits can be reliably initialized according to one from any of these power-on reset signals.